1. Field of the Invention
The present invention relates to a transistor. More particularly it relates to a transistor in which a parasitic transistor is formed in a transistor region, and still more particularly to an improvement of a vertical NPN transistor and a complementary transistor.
2. Description of the Related Art
Conventionally vertical NPN transistors of this kind are manufactured, for example, in the following process. At the outset, as shown in FIG. 8(a), in a predetermined region on the surface of a P-type semiconductor substrate 101, an N.sup.+ -type (a high impurity concentration N-type) buried layer 102 is provided and an N-type epitaxial layer 103 is formed on the entire surface thereof. Subsequently in a region surrounding the N.sup.+ -type buried layer 102 P-type impurity atoms are diffused into the N-type epitaxial layer 103 to form a P.sup.+ -type isolation diffusion layer 104 reaching the substrate 101. Then on the upper portion of the N.sup.+ -type buried layer 102 N-type impurity atoms are diffused to form an N.sup.+ -type diffusion layer 105. In the subsequent step, the N.sup.+ -type diffusion layer 105 is subjected to heat treatment, e.g. for 80 minutes at 900.degree. C. in atmosphere of H.sub.2 O thereby forming an oxide film 106 to a thickness of about 3000 .ANG.. The N+-type diffusion layer 105, the N.sup.+ -type buried layer 102 and the N-type epitaxial layer 103 constitute an N-type collector layer.
Subsequently, as shown in FIG. 8(b), an opening 106a is bored on the upper portion over the N.sup.+ -type buried region 102 out of the oxide film 106. Through this opening 106a .sup.11 B ions (designated by Reference Numeral 107) are implanted to form a P.sup.- -type (a low impurity concentration P-type) active base 108. Then as shown in FIG. 8(c), on the surface of the substrate, a resist 110 is applied, followed by performing photolithography to bore an opening 110a in a region corresponding to the periphery of the active base 108 out of the resist 110. Through this opening 110a .sup.11 B ions are implanted to form a P.sup.+ -type (a high impurity concentration P-type) external base 111 on the periphery of the active base 108 (incidentally out of the active base 108 a portion where P.sup.- type remains is referred to as an "internal base"). After removing the resist 110, as shown in FIG. 9(a), an oxide film 112 is formed on the opening 106a. Then as shown in FIG. 9(b), on a portion corresponding to a portion above the internal base 108a an opening 112a is bored followed by ion implanting As ions to form an N.sup.+ -type emitter region 114 on the surface of the internal base 108a. After this step, as shown in FIG. 9(c), an oxide film 115 is provided on the entire surface. With a known method a collector electrode 116, a base electrode 117 and an emitter electrode 118 are then formed.
This vertical NPN transistor can have a favorable ohmic contact with the base electrode 117 on the high impurity concentration (p.sup.+) external base 111 while controlling the current amplification rate hFE at the low concentration (p.sup.-) internal base 108a.
With respect to the vertical NPN transistor, increasing the impurity concentration at the external base 111 to lower the base resistance will result in a diffusion of P-type impurity element at the external base 111 deep into the N-type epitaxial layer in the transverse direction. Consequently the current amplification rate hFE increases in a parasitic PNP transistor in which the external base 111 serves as an emitter, an N-type epitaxial layer 103 serves as a base and a P.sup.+ type isolation diffusion layer 104 serves as a collector with the result that a latch-up might occur in the operation.
As a means for preventing the latch-up, a spacing between the external base 111 and the P.sup.+ type isolation diffusion region 104 (namely a base width of the above parasitic PNP transistor) is conventionally widened. Furthermore, a high concentration N.sup.+ region is provided between the external base 111 and the P.sup.+ -type isolation diffusion region 104. In any way, a spacing between the external base 111 and the P.sup.+ -type isolation diffusion region is require to be widened. Such case poses a problem that the size of the transistor increases and the production cost thereof also increases.
In addition, conventional CMOS transistors are manufactured with a method shown in FIG. 12. At the outset, as shown in FIG. 12(a), on the surface of a P-type semiconductor substrate 41 N-type impurity elements are diffused in a low concentration to form an N.sup.- -type (a low concentration impurity N-type) deep well 42 followed by forming an oxide film to a thickness of more than several hundred .ANG. over the entire surface of the well. Then a silicon nitride film is deposited thereon with the Chemical Vapor Deposition (CVD) method. Then as shown in FIG. 12(b), the semiconductor substrate is subjected to patterning with the photoetching process in such a manner that the silicon nitride film remains at a portion that will serve as an active region in the later process. This is followed by forming a Local Oxidation of Silicon (LOCOS) oxide film 43 for device isolation. Then a gate oxide film 44 is formed, ions are implanted for the control of the threshold voltage, and then a gate electrode 45 is formed, for example, with a polycrystalline silicon or the like.
In addition, as shown in FIG. 12(c), on the surface of the N- well 42, the source and drain regions of a P channel MOS transistor is subjected to patterning 46 with selfalignment. Then B (boron) ions are implanted under the conditions of acceleration energy of 20 KeV, a dose of 3.times.10.sup.15 ions/cm.sup.2 followed by forming a source region 47 and a drain 48.
Lastly, as shown in FIG. 12(d) after the source/drain regions 49 and 50 are formed with the ion implantation of As (arsenic) in the same manner, source/drain electrodes are formed respectively for the P and N channels with the known method thereby completing a CMOS transistor.
However, in conventional CMOS transistors, as shown in FIG. 12(c), a high concentration of B is ion implanted into the source and drain regions on the P channel side for lowering the resistance. Consequently, the current amplification rate hFE increases in the parasitic PNP transistor in which P+ type source/drain regions 47 and 48 serve as an emitter, the N.sup.- type well 42 serves as a base and the P-type semiconductor substrate 41 serves as a collector with the result that a latch-up mode is generated in the operation.
Then the only method currently available for preventing the latch-up is to widen a distance between the drain region 48 and the semiconductor substrate 41 (a base width in the above parasitic transistor). Such method has a disadvantage that the size of transistors inevitably enlarges and the manufacturing cost thereof increases as well.